This invention relates to data communication systems, and more particularly to a buffer memory and a method of operating a buffer memory in an interface between a host computer and a crossbar switch.
When a number of high-performance processor nodes are to be interconnected to form a network, one of the alternatives is the use of direct connection, as by crossbar switching apparatus. The crossbar switch functions to make physical connections between processor nodes, based upon destination address information sent by a source node in the beginning of a data packet. An interface is usually interposed between each of the host computer nodes and the crossbar switch to provide buffering and to execute a protocol, so the host is relieved of the task of executing the protocol and so that asynchronous transmission and reception of data is allowed. Usually the interface employs transmit and receive FIFOs and a global buffer memory. Data received from a transmission channel is stored in the receive FIFO and later transferred to the global buffer memory for protocol processing, then, after protocol processing, the data is transferred to another FIFO for transmission by the interface circuit to the crossbar or host computer.
The prior interface arrangements for buffering data in high-performance interconnect systems have been limited in throughput, imposing delays in transmitting data at the rates sometimes needed in the highest performance levels. For example, a parallel interface standard is being established which transmits data at 800-Mbps on a 32-bit parallel channel, or at 1600-Mbps on a 64-bit parallel channel; this is referred to as the High-Performance Parallel Interface (HIPPI) standard proposed by American National Standard for Information Systems (ANSI). The HIPPI standard is intended as the physical layer of a simplex high-performance point-to-point interface for transmitting digital data at these high peak data rates between data processing equipment, using 32-bit parallel twisted-pair copper cabling at distances up to 25 meters. The purpose of this parallel interface standard is to provide information exchange meeting the following criteria: content independence, in that the operation is not affected by the contents of information transfers; timing independence, in that the control is not dependent upon timing-critical operation in the upper-layer protocols; and flow control, in that the signal sequences provide look-ahead flow control to allow the average data rate to approach the peak data rate, even over distances longer than that nominally specified. Characteristics of the HIPPI standard include: point-to-point connections using one or two copper twisted-pair cabling; a simplex interface, capable of transfer in one direction only, with two of the interfaces being used to implement a full-duplex interface; data transfers performed and flow-controlled in increments of burst; simple signalling and control sequences with look-ahead flow control; support for low-latency, real-time and variable sized packet transfers; use in a circuit-switched environment is allowed, supported by a limited information field for subdevice addressing, one round-trip delay being required to establish or terminate a connection; multiple packets allowed after a connection is established, with no added delay between packets.
While the high-performance parallel interface standard provides the potential for information transfers between high-speed data processing equipment at very advanced quantitative levels, the burden placed upon the host equipment is substantial. An interface is needed to off-load protocol-related functions from the host computer. In addition to buffering large amounts of data, the interface must be able to execute protocols at various levels, and so relatively unrestricted access to the buffered data in the interface is a necessity.
An ideal crossbar network would act as an "intelligent multiplexer". It would add zero latency to packet transmission, zero latency in making connections, predict data errors and not transmit damaged blocks or maybe correct damaged data "on the fly" (using EEC). It would also adapt instantly to network reconfigurations. Since this ideal is not attainable, the object is to minimize the latency of each component in the network.